You may select Copy Source to Simulation Directory and/or Automatically set simulation compilation file order. Then select Active-HDL for Simulator.Īdd and Reorder Source Files by using the arrows to organize files, you can also add or delete source files. Provide the Project Name and the project location. To start Simulation Wizard, go to Tools | Simulation Wizard You can also use File | New menu to add new files or open existing files and save it to the design directory.Ĭhoose the desired source type, provide a name, and click New.Īfter selecting the source file type, a new editor window will open and will be ready for design entry.Īdd the path for Aldec Simulator by going to Tools | Options and selecting Environment -> Directories under Simulation:, provide the path for Active-HDL. To create a new file or an existing file, right click Input Files and click Add -> New File. The project's file list, process, hierarchy, and the console will also be displayed. If everything is correct, select Finish.Ī Project Summary that includes Reports will be displayed. Project Information with specification that were previously selected will be displayed. Select Synthesis Tool by clicking Lattice LSE for this tutorial. (You can select to Copy source to implementation directory). If you have any source files select Add Source. Provide the Project Name, Project Location, Implementation Name, and Implementation Location. You will then need to request a license to run the Diamond Design Software and request an Aldec license.Īt the start page of the Lattice Diamond, you will be able to create a new Project.Ĭlick on New under Project or click File | New | Project. The free downloads are available here: Active-HDL and Lattice Diamond. You will first need to install Lattice Diamond Design Software and the latest version of Active-HDL to be able to successfully complete this tutorial. In this tutorial we use a sample VHDL design provided by Lattice Diamond to perform design entry and simulation. Active-HDL is an integrated environment designed for development and verification of VHDL, Verilog, System Verilog, EDIF, and System C based designs. This tutorial provides instructions for using Active-HDL in Diamond. Getting Started with Active-HDL in Diamond Introduction
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